The invention relates to color display systems which employ one or more electro-optic display devices. Such a display device serves as a light modulator, either in the reflective or transmissive mode, to control the grey level of projected light at each pixel point. More particularly, the invention relates to such a color display system having ramp generator circuitry for generating a saw-tooth analog signal and circuitry to address the individual pixels of the display device with such an analog signal.
Color display systems are known in which light bars of different colors are sequentially scrolled across a single electro-optic light modulator panel to produce a color display. See, for example, commonly assigned U.S. Pat. No. 5,532,763, incorporated herein by reference.
These display systems are particularly suitable for displaying color information in the form of continuously updated image information signals arranged in successive frames, such as color video information, in which each frame is composed of component color sub-frames, e.g., red, green and blue sub-frames.
These systems employ an electro-optic light modulator panel comprised of a row-and-column matrix array of pixels, for modulating light in accordance with the image information signals during successive frame periods. The analog signal information is applied to the pixel columns of the array, a row at a time, during each frame period.
A system of this type is also disclosed in the publication of J. A. Shimizu, xe2x80x9cSingle Panel Reflective LCD Projectorxe2x80x9d, Projection Displays V, Proceedings SPIE, Vol. 3634, pp. 197-206 (1999). In such a system, a plurality of column pixel driver circuits receive a common ramp signal which is repeatedly generated, during a plurality of cycles, by the output buffer of a digital-to-analog converter (DAC) controlled ramp generator. Each column driver is coupled to all the pixels in a column of the electro-optic display device. During each ramp cycle, the column driver applies a prescribed voltage, corresponding to a desired pixel brightness level, to a pixel in a particular row in the respective column.
The pixels in a column are selected by a row control circuit which selects successive pixel rows during successive ramp cycles.
In a system of this type, the DAC controlled ramp generator and/or the column driver circuits become a performance xe2x80x9cbottleneckxe2x80x9d at higher frame rates (greater than 120 frames/second) which are desirable to reduce color artifacts and flicker. As the frame rate is increased, the finite conversion time (cycle time) of the DAC and the finite switching time of the column drivers pose a limitation on the maximum speed of operation.
The Japanese Patent No. 5-297833 discloses a driving circuit for a display which is similar in many respects to the system described above. In this case, a step wise increasing (or decreasing) waveform is applied to a sample and hold circuit. When the staircase ramp reaches a desired level, this circuit samples and holds that voltage for presentation to a pixel on the display in a particular row. The staircase ramp is generated by two step wise waveform voltage circuits which vary the staircase ramp in course steps and fine steps, respectively.
It is a principal object of the present invention to provide a circuit which will permit an increase in the frame rate in an electro-optic display without increasing the cost of hardware, and without reducing the number of grey levels (brightness levels) which can be applied to each pixel.
This object, as well as other objects which will become apparent from the discussion that follows, are achieved, in accordance with the present invention, by providing a column driver control circuit which enables a selection (sampling) from among two or more analog levels during each basic clock cycle. This is accomplished by selecting from among a plurality of phase-shifted waveforms generated by a multiphase clock.
The present invention thus affords an improvement in speed in a system for applying various levels of voltage to the individual pixels in an electro-optic display device having a matrix of pixels arranged vertically in columns and horizontally in rows. This system includes:
(a) a digital clock for producing a digital clock timing pulse signal at a first clock timing rate;
(b) a digital counter, connected to the digital clock for counting clock timing pulses and repetitively producing a ramp cycle signal upon receipt of a prescribed number of clock pulses;
(c) a ramp generator, coupled to the digital counter for producing a substantially monotonic ramp voltage signal during each ramp cycle;
(d) a number of column drivers, one for each column of the display device, which includes a sampling circuit, coupled to the pixels in the respective column of the display device, for storing the ramp voltage signal when it reaches a prescribed value corresponding approximately to a particular, desired brightness level of a pixel in the respective column and in a particular row during a given ramp cycle;
(e) a column control circuit, coupled to all of the column drivers, for causing respective ones of the sampling circuits to sample and store the ramp voltage signal upon receipt of the next clock timing pulse after the ramp voltage signal reaches the prescribed value for each respective column; and
(f) a row control circuit for repeatedly selecting one or more pixel rows which receive the voltage signals stored in the sampling circuits of the column drivers.
According to the invention, the column control circuit includes (1) a multiphase clock, coupled to the digital clock, for producing a plurality of phase-shifted waveforms, each waveform providing a trigger pulse, for triggering the sampling circuit of the respective column drivers to store the instantaneous ramp voltage signal, and (2) a plurality of column selection circuits, one for each column, for selecting the one of the plurality of waveforms which causes the associated column driver to trigger at the moment when the ramp voltage signal most closely corresponds to the desired brightness level of a particular pixel in the respective column.
Preferably, the digital counter produces a second digital signal which changes in successive steps at the first clock timing pulse rate, during each ramp cycle, and which repeats such changes during a plurality of successive ramp cycles; and the ramp generator includes a digital-to-analog converter (DAC) for producing a first voltage signal having a value corresponding to the second digital signal. This first voltage signal, which may have sudden, stepwise changes in value, can be smoothed by a filter so as to be substantially monotonic during each ramp cycle.
In a preferred embodiment of the present invention, the digital signal source comprises a first clock pulse generator, operating at the first clock timing rate, and a first counter coupled to the first clock pulse generator and supplying a pulse count, during each ramp cycle, to the DAC. In this embodiment, the column control circuit comprises, in combination:
(1) a second clock pulse generator operating at the second clock timing rate;
(2) a second counter, operating at the second clock timing rate and connected to the second clock pulse generator for counting the clock pulses produced thereby;
(3) a plurality of data registers, each associated with one column of the display, for receiving and storing a digital number corresponding to the brightness level of a pixel in a particular row of the associated column;
(4) a comparator, connected to the second counter and to the data register, for comparing the digital numbers in the counter and the register and producing an output signal when the numbers are equal;
(5) a master latch, reset by the clock pulse generator and coupled to the comparator for storing the output signal for one clock period at the first clock timing rate;
(6) a multiphase clock driver connected to the second clock pulse generator for producing a plurality of third clock pulse signals having different phases with respect to each other;
(7) a multiplexer, coupled to receive the plurality of third clock pulse signals from the multiphase clock driver, for selecting one of the third clock pulse signals; and
(8) a plurality of slave latches, each associated with one column of the display and reset by the multiplexer and coupled to the master latch, each slave latch producing a second output signal for controlling one of the column drivers.
This arrangement permits the sampling rate of the column control circuit to be increased by a multiple of the clock pulse rate of the first clock pulse generator, thus increasing the grey scale resolution without increasing the conversion rate of the DAC and/or the speed of operation of the column drivers of the display device.
For a full understanding of the present invention, reference should now be made to the following detailed description of the preferred embodiments of the invention as illustrated in the accompanying drawings.